The present disclosure relates to assuring chip reliability, and more specifically, to assuring chip reliability with generation of chip reliability drivers and assertions based on chip structure identification.
With the shrinking sizes of hardware devices, design susceptibility to soft errors became a significant concern in electrical designs. Most modern designs, from application-specific integrated circuits (ASICs) to microprocessors, contain some degree of Error Detection and/or Correction (EDC) capabilities, often implemented as supplementary logic. In some cases, a design may adhere to very strict reliability requirements and may be designed with an extensive amount of EDC in it such that almost all functional latches may be protected against soft (or hard) errors using hardware error checkers. Different methodologies and techniques are used in order to verify that a given design meets its reliability requirements.
One of these methods is code review, which occurs during the logic implementation phase. The goal of the review process is to make sure that latches in the design are protected according to a corresponding specification. For example, if a specification indicates that a command bus is to be protected by parity checking, the design reviewer will have to make sure that is what was actually implemented in the hardware description (for example, the VHSIC Hardware Description Language (VHDL files)). Since the verification process involves going thru many lines of code across various files, the process can be time-consuming, expensive, and error prone.
Some current methods for chip verification may apply simulation techniques designed to find invariance in the design and to assist functional verification of the design. Further techniques may include fault injection techniques to ensure reliability. Current methods may be general and not configured to improve chip reliability. Furthermore, they may not take advantage of predefined reliability protection structures that exist on modern processing chips. For example, some conventional approaches may include generating assertions for general verification of a chip based on certain specifications provided by the user. This approach often focuses on ranking the generated assertions. These methods may consider reliability verification and may not check the general correctness of a design.
Simulation traces, data mining, and formal verification are also commonly used to automatically identify general assertions that may be invariants of the design. Again, these conventional methods may not consider the reliability of the chip based on prior knowledge about reliability structures, may not seek for general invariants, and do not use simulation traces or data mining to generate the assertions.